ArchViz models a classic in-order, single-issue RISC pipeline — the textbook five stages a RISC-V integer instruction passes through, one stage per clock cycle:

A new instruction is fetched every cycle, so once the pipeline fills, one instruction completes per cycle (an ideal CPI of 1). Real code can't always sustain that — instructions depend on results that aren't ready yet, and branches change where to fetch from. Those are hazards, and resolving them costs cycles:

• Data hazards. A hazard-detection unit watches for an instruction that needs a register an earlier one hasn't written yet. A forwarding unit routes results straight from EX/MEM or MEM/WB back into EX, avoiding most stalls. Toggle forwarding off to watch the bubbles reappear.
• Load-use. A value loaded from memory isn't ready until after MEM, so an instruction that uses it immediately still stalls one cycle, even with forwarding.
• Control hazards. Branches resolve in EX under a predict-not-taken policy; a taken branch squashes the two instructions already fetched behind it (a 2-cycle flush).

The register file writes in the first half of a cycle and reads in the second, so a result reaching write-back is visible to an instruction decoding that same cycle. Supported ISA: the RV32I integer subset — add sub and or xor slt, their -i immediates, lw / sw, beq / bne, and nop — plus a small RV32M-style mul (real RISC-V keeps multiply in its own extension too, since base RV32I has none).

Write a program

Type RISC-V assembly in the editor, or pick an example — each one isolates a particular hazard. It assembles as you type; errors point at the offending line.

Step through time

Use the transport bar to play, pause, step one cycle, jump to the start or end, or drag the scrubber. Adjust the speed slider for playback rate. You can also click any cycle number or cell in the diagram to jump straight there.

Read the diagram

Each row is an instruction; each column a clock cycle. Coloured cells show which stage an instruction occupies. A repeated, hatched cell is a stall; a red ✕ is a flushed instruction. At the selected cycle, arrows show live forwarding.

Forwarding & Plasma

The Forwarding switch re-runs the model with bypass paths on or off. The Plasma switch toggles the magnetohydrodynamic background.

Registers drawer

Open the drawer (top-right) for the live register file and data memory at the selected cycle; values that just changed are highlighted.

Stats

CPI is cycles per retired instruction (closer to 1 is better); stalls and flushes count the bubbles hazards introduced.